The present invention relates generally to design methods for VLSI layouts, and more particularly to methods for improving the performance of VLSI layouts designed by a timing driven physical design tool.
Integrated circuits comprise a collection of components such as transistors, resistors, and capacitors, fabricated on a semiconductor substrate and connected together with metal interconnections, called wires, to form a system such as a microprocessor. Integrated circuit performance has been improving because the components and the wires are being fabricated in smaller sizes to increase the density of the integrated circuits. More and more components and wires are being placed on to each unit area of semiconductor substrate. Parasitic effects in the wires, such as capacitance and resistance, have a more substantial influence on performance as the wires become smaller and are placed closer together. The parasitic effects influence the operating speed and timing of an integrated circuit.
Integrated circuits are classified according to their levels of complexity. Very large-scale integration (VLSI) circuits are the most complex. A VLSI circuit may include an arrangement of gates, also called cells, each of which implements a logic function. Cells may be standardized and selected from a cell library. Examples of cells include an exclusive-OR gate, an AND-OR-INVERT gate, flip-flops, adders, and a read-only memory (ROM). The arrangement of cells is fabricated on a semiconductor substrate and the cells are connected together with wires to complete the integrated circuit.
The performance of the VLSI circuit may substantially depend on its design, and it is designed in a design process. A flowchart of a conventional design process 100 for a VLSI circuit is shown in FIG. 1. A system specification is provided in 110, and in 112 a functional design is developed to carry out the system specification. The functional design is translated into a logic design in 114 and the logic design is verified in 116 in an iterative manner. A circuit design is then constructed based on the logic design with a selection of cells in 118, and the circuit design is verified in 120 in an iterative manner. An early physical design of the VLSI circuit is generated in 122 concurrently with the design and verification procedures 112-120, and the physical design is completed in 124 based on the early physical design and the circuit design. The physical design of the VLSI circuit is a design of the cells and wires that are fabricated in a semiconductor substrate, and includes a placement of the cells and a routing of wires between the cells. The placement of the cells and the routing of the wires comprise a layout of the VLSI circuit, and the layout is verified with reference to the circuit design in 126 in an iterative manner. The VLSI circuit is then fabricated in 128 and packaged and tested in 130.
Physical design tools are software packages used to generate the physical design. Several different types of physical design tools are known to those skilled in the art including floorplanning tools, partitioning tools, placement tools, and routing tools. Placement tools are used to locate the cells in the layout while routing tools are used to route the wires between the cells.
Two primary goals of conventional placement tools are to reduce the area of a semiconductor substrate occupied by an integrated circuit by improving its density, and to improve the timing performance of the integrated circuit. The placement tools reduce a total wire length of a layout to improve its density. In addition a timing-driven placement tool also rearranges the placement of cells to improve timing performance.
As parasitic effects become more significant in limiting the performance of VLSI circuits, placement tools are being used to improve the timing performance of integrated circuits. Conventional placement tools use approximations that may compromise the performance of resulting integrated circuits. For example, conventional placement tools use simplified delay models such as Elmore or lumped RC approximations for wires in a net and estimate the lengths of the wires to compute a delay of the net.
There is a need for a placement tool that creates VLSI circuit layouts with substantially improved timing performance.
According to one embodiment of the present invention a method includes placing cells of a circuit design in a placement of an integrated circuit, routing wires between the cells to complete a layout of the integrated circuit having a number of nets, and analyzing the placement for timing performance. The method also includes, for each cell in the placement, identifying an improved location for the cell based on an estimated savings in delays caused by all of the nets in the layout to a signal propagating through the layout when the cell is placed in the improved location and a net criticality of each net in the layout.